compression IP
The Ocean Logic line of Compression IP includes H.264 Encoder and Limited Decoder, MPEG-4 Encoder and JPEG Encoder and Decoder. All these cores have been proven both in ASIC and FPGA.
MPEG-4 has been phased out in favor of H.264 and JPEG has been acquired by InSilicon Corporation and it is now part of Synopsys DesignWare. Both these two cores are no longer available.
In 2022 we introduced a QOI Lossless Image Compression Encoder and Decoder IP core. These are a low footprint, high performance implementations of the QOI algorithm. Both Encoder and Decoder are capable of processing up to ~800 Mpixels/s in high end FPGAs and more than 4K@30 in low end ones. White paper here.
In 2011 Ocean Logic introduced a new H.264 Baseline Encoder based on Compressed Frame Store (CFS) technology (patents granted in US, China, Japan and Korea) that :
- is compatible with existing H.264 decoders
- allows to compress the refence frames 8-16:1 with no error/drift in the reconstruction when a third party decoder is used
- is
not
restricted to the H.264 standard and it could be potentially
applied to other video compression algorithms
Such a high level of compression allows the CFS to be integrated on the same chip as the encoder. This eliminates the need for power hungry DRAM. Also, because of the high compression, the CFS memory is rarely accessed. This results in extreme low power.
An overview of the benefits and applications of the technology is available here and also here. A Virtual Reality Camera white paper using the CFS technology is available here.
This technology is currently available for licensing as the exclusive license to a large corporation has now expired. This has resulted in a SoC capable of H.264 encoding of 1080p@30 video with I and P frames and without external DRAM. This SoC is available now.
If you wish to evaluate any of our H.264 IP Cores, please contact us to sign an NDA and receive the User's Guide as well as the bit accurate C model. Successful evaluation of the bit accurate C model is a prerequisite for any board or FPGA netlist evaluation.